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Integrated Circuit Systems, Inc.
ICS9250-16
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E type chipset. Output Features: * 3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz achievable through I2C) * 9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz achievable through I2C) * 8 PCI (3.3 V) @33.3MHz * 2 IOAPIC (2.5V) @ 33.3MHz * 2 Hublink clocks (3.3 V) @ 66.6MHz * 2 USB (3.3V) @ 48MHz ( Non spread spectrum) * 1 REF (3.3V) @ 14.318MHz Features: * Supports spread spectrum modulation, down spread 0 to -0.5% and 0.25% center spread. * I2C support for power management * Efficient power management scheme through PD# * Uses external 14.138MHz crystal * Alternate frequency selections available through I2C control.
Pin Configuration
*FS2//REF0 VDD0 X1 X2 GND0 GND1 3V66-0 3V66-1 VDD1 VDD2 PCICLK0 PCICLK1 PCICLK2 GND2 PCICLK3 PCICLK4 GND2 PCICLK5 PCICLK6 PCICLK7 VDD2 VDD3 GND3 GND4 48MHz_0 48MHz_1 VDD4 FS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GNDL1 IOAPIC0 IOAPIC1 VDDL1 CPUCLK0 VDDL0 CPUCLK1 CPUCLK2 GNDL0 GND5 SDRAM0 SDRAM1 VDD5 SDRAM2 SDRAM3 GND5 SDRAM4 SDRAM5 VDD5 SDRAM6 SDRAM7 GND5 SDRAM_F VDD5 PD# SCLK SDATA FS1
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
Block Diagram
X1 X2 XTAL OSC PLL1 Spread Spectrum /2 /3
3
REF0
Functionality
VDDL CPU66/100/133 [2:0] 3V66 [1:0] SDRAM [7:0] SDRAM_F PCICLK [7:0] IOAPIC [1:0] VDDL 48MHz [1:0]
FS2 X X 0 0 1 1
FS1 0 0 1 1 1 1
FS0 0 1 0 1 1 0
ICS9250-16
Function Tristate Test Active CPU = 66MHz SDRAM = 100MHz Active CPU = 100MHz SDRAM = 100MHz Active CPU = 133MHz SDRAM = 100MHz (Special Condition) Active CPU = 133MHz SDRAM = 133MHz
FS(2:0) PD#
Control Logic
2 8
SDATA SCLK Config Reg /2 /2 PLL2
1 8
2
2
9250-16 Rev H 9/5/00 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-16
General Description
The ICS9250-16 is a single chip clock solution for 810/810E type chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-16 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Power Groups
VDD0, GND0 = REF & Crystal VDD1, GND1 = 3V66 (0:1) VDD2, GND2 = PCICLK(0:7) VDD3, GND3 = PLL core VDD4, GND4 = 48MHz (0:1) VDD5, GND5 = SDRAM_F, SDRAM (0:7) VDDL0, GNDL0 = CPUCLK (0:2) VDDL1, GNDL1 = IOAPIC (0:1)
Pin Configuration
PIN NUMBER 1 3 4 5, 6, 14, 17, 23, 24, 35, 41, 47 8, 7 P I N NA M E FS2 REF0 X1 X2 GND (0:5) 3V66 [1:0] TYPE IN OUT IN OUT PWR OUT PWR OUT OUT IN IN IN IN OUT OUT PWR OUT PWR OUT DESCRIPTION Function Select pin. Determines CPU frequency, all output functionality (with 50KW pull-down). 3.3V, 14.318MHz reference clock output. Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V power supply 3.3V PCI clock outputs, with Synchronous CPUCLKS 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. Data input for I2C serial input. Clock input of I2C input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C 3.3V free running 100MHz SDRAM, cannot be turned off through I2C Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending on FS (0:2) pins. 2.5V power supply for CPU & IOAPIC 2.5V clock outputs running at 33.3MHz.
2, 9, 10, 21, VDD (0:5) 22, 27, 33, 38, 44 20,19,18,16, PCICLK[7:0] 15,13,12,11 25, 26 28, 29 30 31 32 36, 37, 39, 40, 42, 43, 45, 46 34 56,48 49,50,52 51, 53 54, 55 48MHz (0:1) FS (0:1) SDATA SCLK PD# SDRAM [7:0] SDRAM_F GNDL [1:0] CPUCLK [2:0] VDDL (0:1) IOAPIC [1:0]
2
ICS9250-16
Power Down Waveform
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
Note
Maximum Allowed Current
810E Condition Powerdown Mode (PWRDWN# = 0 Full Active 66MHz SEL1, 0 = 10 Full Active 100MHz SEL1, 0 = 11 Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND 10mA 70mA 100mA Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND 10mA 310mA 300mA
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 66MHz LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OFF ON VCOs OFF ON
3
ICS9250-16
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
4
ICS9250-16
Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit Bit7 Bit6 Bit5 FS2 (HW) 0 0 0 0 0 0 Bit (3,0) 0 0 1 1 1 1 1 1 1 1 Bit4 Bit2 Bit1 Desctiption ICS RESERVED BIT (Needs to be 0 clock to operate normal) ICS RESERVED BIT (Needs to be 0 clock to operate normal) ICS RESERVED BIT (Needs to be 0 clock to operate normal) Bit (3,0) FS0 (HW) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 (Bit3) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 (Bit0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK SDRAM MHz MHz 66.67 70.00 72.67 74.67 100.00 105.00 109.00 112.01 133.34 140.00 120.00 124.00 133.34 150.00 140.00 132.99 100.00 105.00 109.00 112.00 100.00 105.00 109.00 112.00 133.34 105.00 90.00 124.00 100.00 150.00 140.00 132.99 3V66 MHz 66.60 70.00 72.67 74.66 66.60 70.00 72.67 74.66 88.66 70.00 60.00 82.66 66.60 75.00 70.00 66.60 PCICLK MHz 33.30 35.00 36.33 37.33 33.30 35.00 36.33 37.33 44.33 35.00 30.00 41.33 33.30 37.50 35.00 33.30 0 1 1 XXXX Note 1 PWD 0 0 0
0 = Down Spread Spread Spectrum 0 to -.5% 1 = Center Spread Spread Spectrum .25% Not used (Needs to be 1 for normal clock operation) Not used (Needs to be 1 for normal clock operation)
Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2 defining specific frequency.
5
ICS9250-16
Byte 0: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Pin#
Bit 2 26 1 (Active/Inactive) Bit 1 25 1 (Active/Inactive) Bit 0 49 1 (Active/Inactive) Notes: 1. Do not write in ID bits, these bits are for ICS internal use only. 2. Bit 0 will always read back 0. If readback/rewrite procedure is to perform, user will need to ensure a "1" is written to Bit 0 for CPUCLK2 to maintain running status.
Byte 1: Control Register (1 = enable, 0 = disable)
Name Reserved ID Reserved ID Reserved ID Reserved ID SpreadSpectrum (1=On/0=Off) 48MHz 1 48MHz 0 CPUCLK2
PWD 0 0 0 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 36 37 39 40 42 43 45 46
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
PWD 1 1 1 1 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 18 16 15 13 12 -
Name PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 Reserved
PWD 1 1 1 1 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
6
ICS9250-16
Byte 3: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 4: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
7
ICS9250-16
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND 0.5 V to V DD +0.5 V 0C to +70C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current SYMBOL CONDITIONS VIH VIL IIH VIN = VDD IIL1 VIN = 0 V; Inputs with no pull-up resistors IIL2 VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz IDD3.3OP CL = Max loads; Select @ 66 MHz CL = Max loads; Select @ 100 MHz CL = Max loads; Select @ 133 MHz CL = 0 pF; Select @ 66 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz CL = Max loads; Select @ 66 MHz CL = Max loads; Select @ 100 MHz CL = Max loads; Select @ 133 MHz CL = Max loads Input address VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 1 1 MIN 2 VSS-0.3 -5 -5 -200 TYP MAX VDD+0.3 0.8 5 UNITS V V A A 110 105 130 310 300 350 10 15 20 70 100 130 400 10 16 5 6 27 45 5 5 5 10 10 A MHz nH pF pF pF ms ms ms ns ns mA
2 -100 97 91 100 275 267 278 8 11 13 22 31 37 220 <1 14.318 7
mA
mA
Operating Supply Current
IDD2.5OP
mA
Powerdown Current Input Frequency Pin Inductance Input Capacitance Transition time Settling time
1 1 1 1
IDD3.3PD IDD.25PD Fi Lpin CIN COUT CINX Ttrans Ts TSTAB tPZH,tPZL tPHZ,tPLZ
12
Clk Stabilization Delay
1 1
Guaranteed by design, not 100% tested in production.
8
ICS9250-16
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP2B 1 Output Impedance RDSN2B VO = VDD*(0.5) Output High Voltage VOH2B IOH = -1 mA Output Low Voltage VOL2B IOL = 1 mA VOH @ MIN = 1.0 V IOH2B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL2B Output Low Current VOL @ MAX = 0.3 V Rise Time1 Fall Time
1
MIN 13.5 13.5 2 -27 27 0.4 0.4 45 40
TYP 16 21
MAX UNITS 45 45 V 0.4 V -27 30 1.6 1.6 55 55 175 250 mA mA ns ns % ps ps
-68 -9 54 11 1.1 1.1 49 48 65 90
tr2B tf2B dt2B
1
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, 66, 100 MHz VT = 1.25 V, 133 MHz VT = 1.25 V VT = 1.25 V
Duty Cycle1 Skew window Jitter, Cycle-to-cycle1
1
tsk2B tjcyc-cyc2B
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO = VDD*(0.5) Output Impedance RDSN1B1 VO = VDD*(0.5) Output High Voltage VOH1 IOH = -1 mA Output Low Voltage VOL1 IOL = 1 mA VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 12 12 2.4 -33 30 0.4 0.4 45
TYP 14 14.5
MAX UNITS 55 55 V 0.55 V -33 38 1.6 1.6 55 175 500 mA mA ns ns % ps ps
-108 -9 95 29 1.2 1.2 49 65 120
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
9
ICS9250-16
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP4B VO = VDD*(0.5) Output Impedance RDSN4B1 VO = VDD*(0.5) IOH = -1 mA Output High Voltage VOH4B IOL = 1 mA Output Low Voltage VOL4B VOH @ MIN = 1.0 V IOH4B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL4B Output Low Current VOL @ MAX = 0.3 V Rise Time1 Fall Time
1 1
MIN 9 9 2 -27 27 0.4 0.4 45
TYP 16 20
MAX UNITS 30 30 V 0.4 V -27 30 1.6 1.6 55 250 500 mA mA ns ns % ps ps
-68 -9 54 11 1.1 1.1 49 81 150
tr4B tf4B dt4B tsk4B tjcyc-cyc4B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP3B Output Impedance RDSN3B1 VO = VDD*(0.5) VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 10 10 -54 54 0.4 0.4 45
TYP 12 15 -92 -16 68 29 1 1.5 52 85 120 150
MAX UNITS 24 24 -46 53 1.6 1.6 55 250 250 300 mA mA ns ns % ps ps
tr3 tf3 dt3 tsk3 tjcyc-cyc3
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, 66, 100 MHz VT = 1.5 V, 133 MHz
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
10
ICS9250-16
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN1B1 IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 12 12 2.4 -33 30 0.4 0.4 45
TYP 15 15
MAX UNITS 55 55 V 0.55 V -33 38 2 2 55 500 500 mA mA ns ns % ps ps
-106 -14 94 29 1.3 1.4 51 250 150
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP5B VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN5B1 IOH = -1 mA Output High Voltage VOH15 IOL = 1 mA Output Low Voltage VOL5 VOH @ MIN = 1.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL5 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 20 20 2.4 -29 29 0.4 0.4 45
TYP 29 27
MAX UNITS 60 60 V 0.55 V -23 27 4 4 55 500 1000 mA mA ns ns % ps ps
-54 -11 54 16 1.3 1.6 53 130 465
tr5 tf5 dt5 tjcyc-cyc5 tjcyc-cyc5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks
Duty Cycle Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
11
ICS9250-16
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP3B VO = VDD*(0.5) Output Impedance RDSN3B1 VO = VDD*(0.5) IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP 15 15
MAX UNITS 24 24 V 0.55 V -46 53 1.6 1.6 55 250 mA mA ns ns % ps
-82 -20 95 28 1.1 1.3 53 130
tr3 tf3 dt3 tjcyc-cyc3B
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
Duty Cycle Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
12
ICS9250-16
0ns
10ns
20ns
30ns
40ns
Cycle Repeats CPU 66MHz SDRAM 100MHz 7.5ns 3.3V 66MHz 2.5ns
0.0ns
0ns
10ns
20ns
30ns
40ns
Cycle Repeats CPU 100MHz SDRAM 100MHz 6.0ns 3.3V 66MHz 0.0ns
5.0ns
0ns
10ns
20ns
30ns
40ns
Cycle Repeats CPU 133MHz SDRAM 100MHz 3.3V 66MHz 0.0ns
0.0ns 0.0ns
0ns
10ns
20ns
30ns
40ns
Cycle Repeats 3.3V 66MHz PCI 33MHz
1.5-3.5ns
Group Offset Waveforms
13
ICS9250-16
Group Skews (CPU = 66 MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveform diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN -3 CPU to SDRAM Skew1 Tsk1 CPU-SDRAM CPU @ 1.25 V, SDRAM @ 1.5 V 1 Tw1 CPU-SDRAM 0 Skew Window 1 Tsk1 CPU-3V66 7 CPU to 3V66 Skew CPU @ 1.25 V, 3V66 @ 1.5 V 1 Tw1 CPU-3V66 0 Skew Window 1 -500 SDRAM to 3V66 Skew Tsk1 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 0 Skew Window1 Tw1 SDRAM-3V66 1 Tsk1 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V Tw1 3V66-PCI 0 Skew Window1 1 Tsk1 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 0 Skew Window1 Tw1 IOAPIC-PCI 1 Guaranteed by design, not 100% tested in production.
TYP -2.6 150 7.2 130 100 155 2.4 275 -0.4 0.25
MAX UNITS -2 ns 500 ps 8 ns 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns
Group Skews (CPU = 100 MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveform diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 Tsk2 CPU-SDRAM 4.5 CPU to SDRAM Skew CPU @ 1.25 V, SDRAM @ 1.5 V 0 Skew Window1 Tw2 CPU-SDRAM 1 Tsk2 CPU-3V66 4.5 CPU to 3V66 Skew CPU @ 1.25 V, 3V66 @ 1.5 V Tw2 CPU-3V66 0 Skew Window1 1 Tsk2 SDRAM-3V66 -500 SDRAM to 3V66 Skew SDRAM, 3V66 @ 1.5 V 0 Skew Window1 Tw2 SDRAM-3V66 1 Tsk2 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V Tw2 3V66-PCI 0 Skew Window1 1 Tsk2 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 0 Skew Window1 Tw2 IOAPIC-PCI 1 Guaranteed by design, not 100% tested in production. 1 Guaranteed by design, not 100% tested in production.
TYP 4.9 140 4.8 150 100 155 2.4 275 -0.4 0.25
MAX UNITS 5.5 ns 500 ps 5.5 ns 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns
14
ICS9250-16
Group Skews (CPU = 133 MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveform diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 Tsk3 CPU-SDRAM -500 CPU to SDRAM Skew CPU @ 1.25 V, SDRAM @ 1.5 V 1 Tw3 CPU-SDRAM 0 Skew Window 1 Tsk3 CPU-3V66 -500 CPU to 3V66 Skew CPU @ 1.25 V, 3V66 @ 1.5 V 1 Tw3 CPU-3V66 0 Skew Window 1 -500 SDRAM to 3V66 Skew Tsk3 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 1 0 Skew Window Tw3 SDRAM-3V66 1 Tsk3 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V 1 Tw3 3V66-PCI 0 Skew Window 1 Tsk3 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 1 Tw3 IOAPIC-PCI 0 Skew Window 1 Guaranteed by design, not 100% tested in production.
TYP 70 125 -145 220 100 155 2.4 275 -0.4 0.25
MAX UNITS 500 ps 500 ps 500 ps 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns
15
ICS9250-16
Ferrite Bead VDD
C2 22F/20V Tantalum
C2 22F/20V Tantalum
Ferrite Bead VDD
1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
3.3V Power Route 1 C3 Clock Load 2.5V Power Route
General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces.
2
2
C1
3 4 5 6 7 8 9
C1
2) Make all power traces and ground traces as wide as the via pad for lower inductance.
Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed.
10 11 12
3.3V Power Route
13 14 15 16 17 18 19 20 21
Connections to VDD:
22 23 24 25 26 27 28
= Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load
16
ICS9250-16
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MA X .380 .455 .630 .730 .830
6/1/00 R E VB
J EDE C MO- 118 DOC# 10- 0034
Ordering Information
ICS9250yF-16-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
17
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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